Principal Engineer, Analogue/RF IC Design
- Cambridge
- Posted 26th Jan 2012
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Posted by:
Polytec Personnel
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Salary:
£15k-£40k
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Job Type:
Permanent
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Address:
Orwell House
Cowley Road
Cambridge
CB4 0PP
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Reference:
24769
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Job Description
Our client, based in Cambridge is seeking a Principal Engineer (Analogue RF/IC Design) with extensive experience in the field of ESD protection on chip-level as well as on cell-level. Candidates must also have extensive knowledge of integrated ESD design techniques.
The main responsibilities of the Principal Engineer, Analogue/RF IC Design are:
* To advance our client's IC ESD protection and carry out the design of such systems for future products from system level through to transistor level. The protection circuits include RF, power management and auxiliary I/O Pads.
* To carry out and review, as applicable, the physical implementation of such protection circuits to ensure full functionality and robustness.
* Liaise with the company's foundry interface to evaluate foundry and third party offerings on ESD-protection and to take judgement on any ESD consequences of technological changes in future geometry nodes.
* This principal designer will also be expected to review, oversee and specify design work of other designers who will carry out the design of some parts of such systems.
* To design the circuit and physical implementation of some of the company power management systems
* There will be the opportunity for the successful candidate to extend their activities into other areas of design which he or she may be interested in and is considered to be suitable for.
Person Specification - required
* Extensive experience in the field of ESD protection on chip-level as well as on cell-level
* Excellent knowledge of integrated ESD design techniques, preferably obtained on sub-micron CMOS, semiconductor physics, as well as knowledge of IO-cell design
* Some knowledge of processing technology
* Some understanding of the design of power management circuits, like switched-mode power supplies, battery chargers and linear regulators, on system and transistor level.
Person Specification - Desired
* Knowledge of transistor level of analogue circuits like opamps, comparators, bandgap references etc in deep sub-micron processes.
* Experience in the physical layout of integrated circuits in deep sub-micron processes and understanding of the parasitic effects occurring in such processes.
* Experience in using Cadence Virtuoso and Mentor Calibre design software
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